This application contains subject mater similar to subject matter disclosed in U.S. patent application Ser. No. 09/667,781 filed on Sep. 22, 2000, U.S. Pat. No. 6,342,423 and Ser. No. 09/667,787 filed on Sep. 22, 2000 pending.
The present invention relates to a method of manufacturing semiconductor devices, e.g., MOS-type transistors and integrated circuits comprising such devices, with improved processing methodology resulting in increased reliability and quality, increased manufacturing throughput, and reduced fabrication cost. The present invention is also useful in the manufacture of CMOS semiconductor devices and has particular applicability in fabricating high-denisity integration semiconductor devices with design features below about 0.18 xcexcm, e.g., about 0.15 xcexcm and below.
The escalating requirements for high density and performance associated with ultra large-scale integration (ULSI) semiconductor devices require design features of 0.18 xcexcm and below, such as 0.15 xcexcm and below, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput for economic competitiveness. The reduction of design features to 0.18 xcexcm and below challenges the limitations of conventional semiconductor manufacturing techniques.
As feature sizes of MOS and CMOS devices are reduced into the sub-micron range, so-called xe2x80x9cshort-channelxe2x80x9d effects arise which tend to limit device performance. For n-channel MOS transistors, the major limitation encountered is caused by hot-electronic-induced instabilities. This problem is attributed to high electrical fields between the source and drain, particularly near the drain, such that charge carriers, either electrons or holes, are injected into the gate or semiconductor substrate. Injection of hot carriers into the gate can cause gate oxide charging and threshold voltage instabilities which accumulate over time and greatly degrade device performance. In order to counter and thus reduce such instabilities, lightly-doped source/drain extension type transistor structures have been developed, as described below.
For p-channel MOS transistors of short-channel type, the major limitation on performance arises from xe2x80x9cpunch-throughxe2x80x9d effects which occur with relatively deep junctions. In such instances, there is a wider sub-surface depletion effect and it is easier for the field lines to go from the drain to the source, resulting in the above-mentioned xe2x80x9cpunch-throughxe2x80x9d current problems and device shorting. To minimize this effect, relatively shallow junctions are employed in forming p-channel MOS transistors.
The most satisfactory solution to date of hot carrier instability problems of MOS devices is the provision of lightly- or moderately-doped source/drain extensions driven just under the gate region, while the heavily-doped drain region is laterally displaced away from the gate by use of a sidewall spacer on the gate. Such structures are particularly advantageous because they do not have problems with large lateral diffusion and the channel length can be set precisely.
Several processing sequences or schemes have been developed for the manufacture of source/drain extension-type MOS and CMOS transistors for use in high-density integration applications, with a primary goal of simplifying the manufacturing process by reducing and/or minimizing the requisite number of processing steps. Conventional processing schemes for making such MOS transistors generally employ disposable spacers made of various materials, e.g., polysilicon, silicon oxides, silicon nitrides, silicon oxynitrides, and combinations thereof.
According to one conventional process scheme, a precursor structure comprising a semiconductor substrate of one conductivity type having a layer stack comprising a thin gate oxide layer and an overlying gate electrode formed on a portion of a surface thereof is subjected to ion implantation prior to sidewall spacer formation, for forming lightly- or moderately-doped implants therein. Following post-implantation annealing, sidewall spacers are formed on the pair of opposing side surfaces of the layer stack by first depositing a dielectric spacer material layer over the substrate surfaces and then removing same from the horizontally-oriented regions, i.e., the top surface of the gate electrode layer and the source and drain regions, by means of anisotropic etching. Such processing results in sidewall spacers left on the side surfaces of the gate layer stack that have an approximately quarter-circular shaped cross-section. The dielectric sidewall spacers typically remain through the balance of junction formation processing. After sidewall spacer formation, a heavy source/drain implantation is performed, with the gate layer stack and associated sidewall spacers acting as implantation masking materials. As a consequence of the separate implantations, the heavily-doped source/drain regions are laterally displaced from the gate edges by the thickness of the sidewall spacer material and the lightly- or moderately-doped regions beneath the sidewall spacers act as source/drain extensions.
According to another conventional process scheme employing disposable (i.e., removable) sidewall spacers, a precursor structure as described above and comprising a semiconductor substrate of one conductivity type having a layer stack comprising a thin gate oxide layer and an overlying gate electrode layer formed on a portion of a surface thereof is subjected to blanket-type dielectric layer deposition and patterning to form sidewall spacer layers on opposing side surfaces of the layer stack. Opposite conductivity type p- or n-type dopant impurities are then implanted into the substrate using the layer stack with sidewall spacers formed thereon as an implantation mask, to thereby form moderately- to heavily-doped implants. High temperature annealing is then performed to thermally activate the implanted dopant by diffusion and reduce lattice damage due to implantation, thereby forming source/drain regions and junctions at a predetermined dopant density and depth below the substrate surface. The effective length of the channel of such transistors is determined by the width of the gate insulator/gate electrode layer stack and the width of the sidewall spacers formed thereon. After activation annealing, the sidewall spacers are removed, as by etching, and a second implantation process for implanting n- or p-type opposite conductivity type dopant impurities is performed using only the gate insulating layer/gate electrode layer stack as an implantation mask, thereby forming shallow-depth, lightly- or moderately-doped implants in the substrate in the spaces between the deeper, more heavily-doped source/drain regions. Following this implantation, a second activation process, e.g., rapid thermal annealing (RTA), is performed for effecting dopant diffusion/activation and relaxation of implantation-induced lattice damage of the implants, to form shallow-depth, lightly- or moderately-doped source/drain extensions extending from respective proximal edges of the heavily-doped source/drain regions to just below the respective proximal edges of the gate insulator layer/gate electrode layer stack.
In a variant of the above-described process, the sidewall spacers are comprised of a layer of a first (or inner) dielectric material and a layer of a second (or outer) dielectric material. According to this variant, only the second, or outer, dielectric sidewall spacer layer is removed subsequent to annealing for forming the moderately- to heavily-doped source/drain regions. The first, or inner, dielectric sidewall spacer layer is retained for protecting the gate insulator/gate electrode layer stack during subsequent processing, e.g., for contact formation.
Each of the above-described variants employ removable. sidewall spacers as part of an implantation mask for defining the channel lengths, and each incurs a drawback in that the materials conventionally used for the sidewall spacers, such as those mentioned above, frequently are difficult and time consuming to remove and remove selectively by standard etching methodologies, particularly when densified as a result of high temperature processing for post-implantation annealing for dopant activation/lattice damage relaxation. For example, and as described in U.S. Pat. No. 5,766,991, removal of silicon nitride-based spacer layers can require etching in a hot phosphoric acid (H3PO4) bath at about 180xc2x0 C. for approximately 1.5 hours. Such long etching time results in reduced manufacturing throughput and the extended exposure to and concomitant attack by the corrosive etchant at high temperature results in undesired etching and defect formation. Moreover, portions of the workpiece substrate not intended to be etched must be provided with an etch-resistant protective barrier layer, e.g., of silicon oxide, prior to etching. However, the etching resistance of the silicon oxide layer itself to the hot H3PO4 may be insufficient, in which case the resistance thereof must be increased prior to etching, e.g., by first annealing it at about 900xc2x0 C. in an oxygen ambient. Alternatively, resistance to attack by the hot H3PO4 may be obtained by use of an oxide-polysilicon bi-layer. In either case, such requirement for provision of at least one layer for protecting from acid attack disadvantageously adds processing time, complexity, and fabrication cost. Etching of annealed, densified silicon oxide and/or silicon oxynitride-based sidewall spacer layers is similarly difficult.
Thus a need exists for improved semiconductor manufacturing methodology for fabricating MOS and CMOS transistors which does not suffer from the above-described drawbacks associated with the difficulty in conveniently and rapidly removing densified sidewall spacers according to conventional etching techniques. Moreover, there exists a need for an improved process for fabricating MOS transistor-based devices which is fully compatible with conventional process flow and provides increased manufacturing throughput and product yield.
The present invention fully addresses and solves the above-described problems and drawbacks attendant upon conventional processing for forming submicron-dimensioned MOS and CMOS transistors for use in high-density semiconductor integrated circuit devices, particularly in providing a process utilizing first (or inner) and second (or outer) dielectric sidewall spacer layers, the second, or outer, spacers being formed of a dielectric material which is selectively subjected to a post-formation treatment for increasing the etchability thereof vis-à-vis that of its as-deposited state, wherein the treated second, or outer, spacers are removed prior to any post-implantation thermal annealing treatment for dopant activation/lattice damage relaxation which may densify and thus increase the etching resistance thereof. The first, or inner, spacers are formed of a dielectric material and are retained throughout processing for protecting the gate insulator/gate electrode layer stack from attack by corrosive etchant and during subsequent ohmic contact formation. In embodiments according to the present invention, the first (inner) and second (outer) sidewall spacers are formed of the same dielectric material, and thus effectively constitute a single spacer; whereas, in other embodiments according to the present invention, single sidewall spacers are formed of a single dielectric material, and only the outer portions thereof are subjected to ion implantation for selectively augmenting the etch rate thereof.
An advantage of the present invention is an improved method for manufacturing MOS and/or CMOS transistor devices utilizing a removable spacer.
Another advantage of the present invention is an improved method for increasing the etchability of dielectric spacer materials utilized in the manufacture of MOS, CMOS, and other types of semiconductor devices.
Yet another advantage of the present invention is an improved method for manufacturing MOS and/or CMOS transistor devices utilizing a removable sidewall spacer formed of a readily etchable dielectric material.
Still another advantage of the present invention is an improved method of manufacturing submicron-dimensioned MOS transistors for use in high-density semiconductor integrated circuit devices at lower cost, higher manufacturing throughput, and increased product yield and reliability than are obtainable with conventional process methodology.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the instant invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to an aspect of the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, which method comprises the steps of:
(a) providing a device precursor structure comprising a semiconductor substrate of a first conductivity type and a layer stack formed on a portion of a surface of the substrate, the layer stack comprising:
i. a thin gate insulating layer in contact with the substrate surface; and
ii. a gate electrode layer formed on the gate insulating layer, the layer stack comprising a pair of opposing side surfaces and a top surface;
(b) forming a first, relatively narrow, insulative, tapered sidewall spacer on each of the pair of opposing side surfaces, the first sidewall spacers comprising a first dielectric material;
(c) forming a second, relatively wider, insulative, tapered sidewall spacer on each of the first sidewall spacers, the second sidewall spacers comprising a second dielectric material having an as-deposited etch resistance, said first and second dielectric materials of said first and second sidewall spacers being the same or different;
(d) treating the second sidewall spacers with impurities to reduce the etch resistance of the second dielectric material from its as-deposited state to a more readily-etched state;
(e) introducing dopant impurities of a second, opposite conductivity type into exposed portions of the substrate surface adjacent the first and second sidewall spacers to form a pair of spaced-apart, heavily-doped regions in the substrate;
(f) etching to selectively remove the impurity-treated second sidewall spacers;
(g) treating the pair of spaced-apart, heavily-doped regions to form a pair of heavily-doped source/drain regions in the substrate having a junction therewith at a predetermined depth below the substrate surface, each of the heavily-doped source/drain regions being laterally spaced from a respective proximal edge of the gate insulating layer by a distance substantially equal to the combined width of the lower ends of the first and second sidewall spacers adjacent the substrate surface;
(h) introducing second, opposite conductivity type dopant impurities into exposed portions of the substrate surface intermediate the gate insulating layer or the first sidewall spacers and the heavily-doped source/drain regions to form lightly- or moderately-doped extension regions; and
(i) treating the lightly- or moderately-doped extension regions to form a pair of shallow-depth, lightly- or moderately-doped source/drain extensions in the substrate, each of the shallow-depth, lightly-doped source/drain extensions extending from a proximal edge of a respective heavily-doped source/drain region to just beneath a respective proximal edge of the gate insulating layer.
In embodiments according to the present invention, step (a) comprises providing a silicon wafer substrate of n or p first conductivity type, the thin gate insulating layer comprises a silicon oxide layer about 25-50 xc3x85 thick, and the gate electrode layer comprises heavily-doped polysilicon; step (b) comprises forming the first, relatively narrow, sidewall spacers from a dielectric material selected from silicon oxides, silicon nitrides, and silicon oxynitrides, each of the first, relatively narrow, tapered sidewall spacers having a width profile varying from up to about 200 xc3x85 at the lower end thereof adjacent the substrate surface to up to about 100 xc3x85 at the upper end thereof; step (c) comprises forming the relatively wider, second sidewall spacers from a dielectric material having an as-deposited etch resistance and selected from UV-nitrides and silicon oxides, nitrides, and oxynitrides, the UV-nitride dielectric material being formed by chemical vapor deposition (CVD), each of the second, relatively wider, tapered sidewall spacers having a width profile varying from about 100 to about 1,000 xc3x85 at the lower end thereof adjacent the substrate surface to up to about 400 xc3x85 at the upper end thereof, step (d) comprises ion implantation of the second sidewall spacers, comprising implanting ions selected from Si+, Ge+, and p and n type dopant ions at dosages of from about 1xc3x971014 to about 5xc3x971015 ions/cm2 and energies of from about 1 to about 250 KeV; step (e) comprises implanting dopant ions of second, opposite conductivity type at dosages of from about 5xc3x971014 to about 5xc3x971015 ions/cm2 and energies of from about 1 to about 250 KeV; step (f) comprises selectively removing the ion-implanted, reduced etching resistance second insulative sidewall spacers by etching with an HF-containing etchant, e.g., etching at a removal rate of from about 0.3 to about 5 xc3x85/min. with 1:100 HF/H2O at about 20-35xc2x0 C.; step (g) comprises rapid thermal annealing (RTA) to diffuse and activate the second conductivity type dopant impurities introduced during step (e) to form the pair of heavily-doped source/drain regions, each having a junction depth of from about 500 to about 2,000 xc3x85 below the substrate surface; step (h) comprises selectively implanting dopant ions of second conductivity type at dosages of from about 5xc3x971013 to about 1xc3x971015 atoms/cm2 and energies of from about 0.2 to about 30 KeV; and step (i) comprises annealing, e.g., RTA to diffuse and activate the second conductivity type dopant impurities introduced during step (h) to form the pair of shallow-depth, lightly- or moderately-doped source/drain extensions, each having a shallow junction depth of from about 100 to about 1,000 xc3x85 below the substrate surface.
According to a further embodiment of the present invention, steps (d) and (e) are performed simultaneously by implanting dopant impurities of second, opposite conductivity type.
According to another aspect of the present invention, a method of manufacturing a silicon-based MOS-type transistor is provided, which method comprises the steps of:
(a) providing a MOS transistor precursor structure comprising a silicon semiconductor wafer substrate of a first conductivity type and a layer stack formed on a portion of a surface of the wafer, the layer stack comprising:
i. a thin gate insulating layer comprising a silicon oxide layer about 25-50 xc3x85 thick in contact with the wafer surface; and
ii. a gate electrode layer comprising heavily-doped polysilicon formed on the gate insulating layer, the layer stack comprising a pair of opposing side surfaces and a top surface;
(b) forming a first, relatively narrow, insulative, tapered sidewall spacer on each of the pair of opposing side surfaces, the first sidewall spacers comprising a dielectric material selected from silicon oxides, silicon nitrides, and silicon oxynitrides;
(c) forming a second, relatively wider, insulative, tapered sidewall spacer on each of the first sidewall spacers, the second sidewall spacers comprising a UV-nitride dielectric material having an as-deposited etch resistance;
(d) implanting the second sidewall spacers with impurities to reduce the etch resistance from its as-deposited state to a more readily-etched state;
(e) implanting dopant impurities of a second, opposite conductivity type into exposed portions of the substrate surface adjacent the first and second sidewall spacers to form a pair of spaced-apart, heavily-doped implants in the wafer;
(f) etching with dilute aqueous HF to selectively remove the reduced etching resistance second pair of sidewall spacers;
(g) annealing to diffuse and activate the dopant impurities implanted in step (e), thereby forming a pair of heavily-doped source/drain regions in the wafer substrate having a junction therewith at a predetermined depth below the wafer surface and being laterally spaced from a respective proximal edge of the gate insulating layer by a distance substantially equal to the combined width of the lower ends of the first and second sidewall spacers adjacent the wafer surface;
(h) implanting second, opposite conductivity type dopant impurities into exposed portions of the wafer surface intermediate the gate insulating layer or the first sidewall spacer and the heavily-doped source/drain regions to form lightly- or moderately-doped extension regions; and
(i) rapid thermal annealing to diffuse and activate the dopant impurities implanted in step (h), thereby forming a pair of shallow-depth, lightly- or moderately-doped source/drain extensions extending from a proximal edge of a respective source/drain region to just beneath a respective proximal edge of the gate insulating layer.
According to yet another aspect of the present invention, silicon-based MOS-type transistor devices formed by the method of the above-enumerated steps (a)-(i) are provided.
Additional advantages and aspects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the method of the present invention. As will be described, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as limitative.